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zondag, mei 13, 2012

MIPS unveils new Aptiv mobile chip design, vows more speed in a tiny space

MIPS Technologies Introduces New Aptiv? Generation of Microprocessor Cores

MIPS Raises the Performance Bar with New
microAptiv?, interAptiv? and proAptiv? Families

SUNNYVALE, Calif. - May 10, 2012 -

News Highlights:

* A new generation of processor cores offering a high level of performance and efficiency for applications across the home entertainment, networking, mobile and embedded segments

* High-performance proAptiv? core achieves the highest CoreMark/MHz score reported for any licensable IP core, together with leading silicon efficiency

* Multi-threaded interAptiv? core delivers leading performance efficiency, achieving higher CoreMark/MHz than competing cores in similar die area

* Highly-efficient microAptiv? core achieves highest CoreMark/MHz score among microcontroller-class cores; adds DSP acceleration and security

* Several lead licensees already signed for AptivTM cores

MIPS Technologies, Inc. (NASDAQ: MIPS), a leading provider of industry-standard processor architectures and cores for home entertainment, networking, mobile and embedded applications, today introduced a new generation of microprocessor cores. The Aptiv Generation cores, including the proAptiv, interAptiv and microAptiv families, offer three distinct performance levels for applications across MIPS' target segments.

All based on the MIPS32� Release 3 architecture, the products are targeted to build on MIPS' leadership position in home entertainment, strengthen its position in networking, extend the company's offering in the high-volume embedded systems segment, and provide a highly-competitive alternative for mobile system development. For mobile devices, the Aptiv Generation offers top-end multicore performance for applications processing in products including tablets and smartphones, efficient multi-threading technology for applications such as baseband processing, and entry-level performance for embedded control and applications such as touchscreen controllers, SIM/security and GPS.

proAptiv Family Key Features

* Leading high-end CPU performance efficiency delivering over 4.4 CoreMark/MHz and
3.5 DMIPS/MHz1 in considerably smaller area compared to competing IP cores2

* Ideal for applications processing in connected consumer electronics such as high-end mobile devices and "smart" home entertainment products, and control plane processing in networking applications

* Efficient top-end performance minimizes the need for exotic power management schemes such as "big.LITTLE" in many mobile applications

* 60-75% higher performance on CoreMark and DMIPS scores compared to MIPS32 74K?/1074K? superscalar single/multicore products

* Highly-scalable solution leveraging up to six cores connected in a multi-core Coherent Processing System (CPS)

Major architectural features and enhancements:

* High-performance multi-issue, deeply out-of-order (OoO) architecture with state-of-the-art branch prediction

* New higher-performance floating point unit (FPU) with higher synthesizable frequency for 1:1 clock with core and native double-precision execution

* Single-core and multi-core (up to six core) configurations

* Performance-enhanced, tightly-integrated second generation Coherence Manager and L2 cache controller with lower total latency

* MIPS Digital Signal Processing (DSP) Application Specific Extension (ASE) v2

* Enhanced Virtual Address (EVA) for efficient 32-bit address map utilization to reach 3GB+ user space

interAptiv Family Key Features

* The interAptiv core leverages a balanced nine-stage pipeline with multi-threading to deliver leading performance efficiency, achieving greater than 50% more CoreMark/MHz than competing cores in similar die area1,2

* Ideal for highly-parallel applications requiring cost and power optimization, such as smart gateways, baseband processing in LTE user equipment and small cells, SSD controllers and automotive equipment

* Highly-scalable solution leveraging one or more threads per core, and up to four cores connected in a multi-core Coherent Processing System (CPS)

Features and enhancements

* Multi-threaded pipeline implements dual virtual processors, appearing as two complete CPUs to an SMP Linux operating system

* Hardware Quality of Service (QoS), thread management support and inter-thread communication enable optimal control for real-time applications

* Performance-enhanced, tightly-integrated second generation Coherence Manager and L2 cache controller with lower total latency

* Support for up to two I/O coherency units

* Core and CPS-level power management features

* Error Checking and Correction (ECC) support in L1 data cache, L2 cache and data SPRAM

* Enhanced Virtual Address (EVA) for efficient 32-bit address map utilization to reach 3GB+ user space

* Optional floating point unit

microAptiv Family Key Features

* Low-power, compact, real-time embedded processor core with integrated standard I/O interfaces, building on popular MIPS32 M14KTM core family with microMIPSTM code compression instruction set architecture

* Integrates DSP and SIMD functionality to address signal processing requirements for a wide range of embedded segments including industrial control, smart meters, automotive and wired/wireless communications

* Leverages highly-efficient 5-stage pipeline to achieve 3.09 CoreMark/MHz and 1.57 DMIPS/MHz1 in microMIPS mode, with 40% and 25% higher performance, respectively, compared to competition2
MCU and MPU (with integrated cache controller/MMU) product versions available for microcontroller and embedded applications

* Compared to previous generation MIPS cores and competitive cores, offers greater range of design features for both control and DSP operations

* New memory protection unit for enhanced program code and data security, microMIPS-only execution mode, secure debug and 2-wire cJTAG support


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